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TABLE OF CONTENTS GENERAL DESCRIPTION ........................................................................................................................... 1 FEATURES ................................................................................................................................................... 1 ORDERING INFORMATION ........................................................................................................................ 2 BLOCK DIAGRAM ....................................................................................................................................... 3 SSD1332U1R1 COF PACKAGE DIMENSIONS .......................................................................................... 4 SSD1332U1R1 COF PIN ASSIGNMENT..................................................................................................... 5 PIN DESCRIPTION....................................................................................................................................... 7 FUNCTIONAL BLOCK DESCRIPTIONS..................................................................................................... 9 COMMAND TABLE .................................................................................................................................... 12 COMMAND DESCRIPTIONS ..................................................................................................................... 14 MAXIMUM RATINGS ................................................................................................................................. 16 DC CHARACTERISTICS............................................................................................................................ 16 AC CHARACTERISTICS............................................................................................................................ 17 APPLICATION EXAMPLE ......................................................................................................................... 21
TABLE OF FIGURES Figure 1 - Block Diagram .............................................................................................................................. 3 Figure 2 - SSD1332U1R1 COF pin assignment ........................................................................................... 5 Figure 3 - Oscillator Circuit............................................................................................................................ 9 Figure 4 - Display data read back procedure - insertion of dummy read.................................................... 10 Figure 5 - 6800-series MPU parallel interface characteristics .................................................................... 18 Figure 6 - 8080-series MPU parallel interface characteristics .................................................................... 19 Figure 7 - Serial interface characteristics.................................................................................................... 20 Figure 8 - Application Example for SSD1332U1R1 .................................................................................... 21 LIST OF TABLES Table 1 - Ordering Information ...................................................................................................................... 2 Table 2 - SSD1332U1R1 COF pin assignment ............................................................................................ 6 Table 3 - Command table (D/C# =0, R/W#(WR#)=0, E (RD#)=1) .............................................................. 12 Table 4 - Maximum Ratings (Voltage Reference to VSS) ............................................................................ 16 Table 5 - DC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD = 2.4 to 3.5V, TA = 25C) ............................................................................................................................................ 16 Table 6 - AC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD = 2.4 to 3.5V, TA = 25C.) ........................................................................................................................................... 17 Table 7 - 6800-Series MPU Parallel Interface Timing Characteristics (VDD - VSS = 2.4 to 3.5V, TA = -30 to 85C) .................................................................................................................................................... 18 Table 8 - 8080-Series MPU Parallel Interface Timing Characteristics (VDD - VSS = 2.4 to 3.5V, TA = -30 to 85C) .................................................................................................................................................... 19 Table 9 - Serial Interface Timing Characteristics (VDD - VSS = 2.4 to 3.5V, TA = -30 to 85C) .................... 20
SOLOMON SOLOMON SYSTECH LIMITED
SEMICONDUCTOR TECHNICAL DATA
SSD1332
Product Preview
OLED/PLED Segment/Common Driver with Controller
CMOS
General Description
SSD1332 is a single-chip CMOS OLED/PLED driver with controller for organic/polymer light emitting diode dot-matrix graphic display system. SSD1332 consists of 288 segments (96RGB) and 64 commons. This IC is designed for Common Cathode type OLED panel. SSD1332 displays data directly from its internal 96x64x16 bits Graphic Data RAM (GDDRAM). Data/Commands are sent from general MCU through the hardware selectable 6800/8000 series compatible Parallel Interface or Serial Peripheral Interface. SSD1332 has a 256 steps contrast control and 65K color control.
FEATURES
Support max. 96RGB x 64 matrix panel Power supply: VDD=2.4V - 3.5V VCC=8.0V - 18.0V OLED driving output voltage, 16V maximum DC-DC voltage converter Segment maximum source current: 200uA Common maximum sink current: 50mA Embedded 96x64x16 bit SRAM display buffer 16 step master current control, and 256 step current control for the three color components Programmable Frame Rate Graphic Acceleration Command Set (GAC) 8-bit 6800-series Parallel Interface, 8-bit 8080-series Parallel Interface, Serial Peripheral Interface. Wide range of operating temperature: -30 to 85 C
This document contains information on a new product under definition stage. Solomon Systech Ltd. reserves the right to change or discontinue this product without notice. Copyright 2003 SOLOMON Systech Limited Rev 0.23 08/2003
ORDERING INFORMATION
Table 1 - Ordering Information
Ordering Part Number SSD1332U1R1 Package Form COF MPQ 100
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BLOCK DIAGRAM
3
RES# CS# D/C# E (RD#) R/W#(WR#) BS2 BS1 BS0 VDD VSS D7 D6 D5 D4 D3 D2 D1 D0 Command Decoder MCU Interface Oscillator Display Timing Generator GDDRAM DC-DC voltage converter Grey Scale Decoder Seg/Com OLED Driving block Common Drivers (odd) Segment Drivers Common Drivers(even) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . | | | COM1 COM3 COM61 COM63 COM2 COM0 COM62 COM60 SA0 SB0 SC0 SA1 SB1 SC1 SA95 SB95 SC95
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CL CLS
GDR RESE FB VBref
Figure 1 - Block Diagram
VCC
VCOMH VREF VPA VPB VPC IREF
VSL VCL
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SSD1332U1R1 COF PACKAGE DIMENSIONS
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SD
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SSD1332U1R1 COF PIN ASSIGNMENT
100
Figure 2 - SSD1332U1R1 COF pin assignment
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1332U1R1
NC VCC VCOMH NC D7 D6 D5 D4 D3 D2 D1 D0 E(RD#) R/W#(WR#) D/C# RES CS# IREF BS2 BS1 VDD VP_C VP_B VP_A VBREF RESE FB VDDB GDR VSS NC
COF pin #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
1332U1R1 NC NC NC COM63 COM61 COM59 COM57 COM55 COM53 COM51 COM49 COM47 COM45 COM43 COM41 COM39 COM37 COM35 COM33 COM31 COM29 COM27 COM25 COM23 COM21 COM19 COM17 COM15 COM13 COM11 COM9 COM7 COM5 COM3 COM1 NC NC NC NC NC NC
COF pin # 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
1332U1R1 SC95 SB95 SA95 SC94 SB94 SA94 SA93 SB93 SC93 SC92 SB92 SA92 SC91 SB91 SA91 SC90 SB90 SA90 SC89 SB89 SA89 SC88 SB88 SA88 SC87 SB87 SA87 SC86 SB86 SA86 SC85 SB85 SA85 SC84 SB84 SA84 SC83 SB83 SA83 SC82 SB82 SA82 SC81 SB81 SA81 SC80 SB80 SA80 SC79 SB79 SA79 SC78 SB78 SA78 SC77 SB77 SA77 SC76 SB76 SA76 SC75 SB75 SA75 SC74 SB74 SA74 SC73 SB73 SA73 SC72 SB72 SA72 SC71
COF pin #
73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145
1332U1R1 SC63 SB63 SA63 SC62 SB62 SA62 SC61 SB61 SA61 SC60 SB60 SA60 SC59 SB59 SA59 SC58 SB58 SA58 SC57 SB57 SA57 SC56 SB56 SA56 SC55 SB55 SA55 SC54 SB54 SA54 SC53 SB53 SA53 SC52 SB52 SA52 SC51 SB51 SA51 SC50 SB50 SA50 SC49 SB49 SA49 SC48 SB48 SA48 SC47 SB47 SA47 SC46 SB46 SA46 SC45 SB45 SA45 SC44 SB44 SA44 SC43 SB43 SA43 SC42 SB42 SA42 SC41 SB41 SA41 SC40 SB40 SA40 SC39
COF pin #
169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241
1332U1R1 SC31 SB31 SA31 SC30 SB30 SA30 SC29 SB29 SA29 SC28 SB28 SA28 SC27 SB27 SA27 SC26 SB26 SA26 SC25 SB25 SA25 SC24 SB24 SA24 SC23 SB23 SA23 SC22 SB22 SA22 SC21 SB21 SA21 SC20 SB20 SA20 SC19 SB19 SA19 SC18 SB18 SA18 SC17 SB17 SA17 SC16 SB16 SA16 SC15 SB15 SA15 SC14 SB14 SA14 SC13 SB13 SA13 SC12 SB12 SA12 SC11 SB11 SA11 SC10 SB10 SA10 SC9 SB9 SA9 SC8 SB8 SA8 SC7
COF pin #
265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337
1332U1R1 NC NC NC NC NC NC COM0 COM2 COM4 COM6 COM8 COM10 COM12 COM14 COM16 COM18 COM20 COM22 COM24 COM26 COM28 COM30 COM32 COM34 COM36 COM38 COM40 COM42 COM44 COM46 COM48 COM50 COM52 COM54 COM56 COM58 COM60 COM62 NC NC NC
COF pin # 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401
Table 2 - SSD1332U1R1 COF pin assignment
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PIN DESCRIPTION
BS0, BS1, BS2 These pins are MCU interface selection input. See the following table:
6800-parallel interface (8 bit) 0 0 1 8080-parallel interface (8 bit) 0 1 1 Serial interface 0 0 0
BS0 BS1 BS2
CS# This pin is the chip select input. The chip is enabled for MCU communication only when CS# is pulled low. RES# This pin is reset signal input. When the pin is low, initialization of the chip is executed. D/C# This pin is Data/Command control pin. When the pin is pulled high, the data at D7-D0 is treated as display data. When the pin is pulled low, the data at D7-D0 will be transferred to the command register. For detail relationship to MCU interface signals, please refer to the Timing Characteristics Diagrams. R/W#(WR#) This pin is MCU interface input. When interfacing to a 6800-series microprocessor, this pin will be used as Read/Write (R/W#) selection input. Read mode will be carried out when this pin is pulled high and write mode when low. When 8080 interface mode is selected, this pin will be the Write (WR#) input. Data write operation is initiated when this pin is pulled low and the chip is selected. When serial interface is selected, this pin E(RD#) must be connected to VSS. E (RD#) This pin is MCU interface input. When interfacing to a 6800-series microprocessor, this pin will be used as the Enable (E) signal. Read/write operation is initiated when this pin is pulled high and the chip is selected. When connecting to an 8080-microprocessor, this pin receives the Read (RD#) signal. Data read operation is initiated when this pin is pulled low and the chip is selected. When serial interface is selected, this pin E(RD#) must be connected to VSS. D7-D0 These pins are 8-bit bi-directional data bus to be connected to the microprocessor's data bus. VDD Power Supply pin. This is also the reference for the OLED driving voltages. It must be connected to external source. VSS Ground. It also acts as a reference for the logic pins. It must be connected to external ground.
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VCC This is the most positive voltage supply pin of the chip. It is supplied either by external high voltage source or internal booster VREF This pin is the reference for OLED driving voltages. It can be either supplied externally or connected to VCC. VPA, VPB, VPC These pins are the driving voltages for OLED driving segment pins SA0-SA95, SB0-SB95 and SC0-SC95 respectively. IREF This pin is segment output current reference pin. A resistor should be connected between this pin and VSS. Set the current at 10uA. VCOMH This pin is the input pin for the voltage output high level for COM signals. A capacitor should be connected between this pin and VSS. VDDB This is power pin. It should be connected to VDD. VSSB This is ground pin. It must be connected to external ground. GDR This is used for testing purpose. It should be left open under normal operation. RESE This is used for testing purpose. It should be left open under normal operation. VBREF This is used for testing purpose. It should be left open under normal operation. FB This is used for testing purpose. It should be left open under normal operation. COM0-COM63 These pins provide the Common switch signals to the OLED panel. These pins are in high impedance state when display is off. SA0-SA95, SB0-SB95, SC0-SC95 These pins provide the OLED segment driving signals. These pins are in high impedance state when display is off. The 396 segment pins are divided into 3 groups, SA, SB and SC. Each group can have different color settings for color A, B and C.
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FUNCTIONAL BLOCK DESCRIPTIONS
Oscillator Circuit and Display Time Generator
Internal Oscillator CL
M U X CLK Divider DCLK Internal Display Clock
Figure 3 - Oscillator Circuit
This module is an On-Chip low power RC oscillator circuitry (Figure 3). The oscillator generates the clock for the Display Timing Generator.
Reset Circuit When RES# input is low, the chip is initialized with the following status: 1. Display is OFF 2. 64 mux Display Mode 3. Normal segment and display data column address and row address mapping (SEG0 mapped to address 00H and COM0 mapped to address 00H) 4. Shift register data clear in serial interface 5. Display start line is set at display RAM address 0 6. Column address counter is set at 0 7. Normal scan direction of the COM outputs 8. Master contrast control register is set at 16H 9. Individual contrast control registers of color A, B, and C are set at 80H
Command Decoder and Command Interface This module determines whether the input data is interpreted as data or command. Data is interpreted based upon the input of the D/C# pin. If D/C# pin is high, data is written to Graphic Display Data RAM (GDDRAM). If it is low, the input at D7-D0 is interpreted as a Command and it will be decoded and be written to the corresponding command register.
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MPU Parallel 6800-series Interface The parallel interface consists of 16 bi-directional data pins (D0-D15), R/W#(WR#), D/C#, E (RD#) and CS#. R/W#(WR#) input High indicates a read operation from the Graphic Display Data RAM (GDDRAM) or the status register. RW#/(WR#) input Low indicates a write operation to Display Data RAM or Internal Command Registers depending on the status of D/C# input. The E(RD#) input serves as data latch signal (clock) when high provided that CS# is low and high respectively. Refer to Figure 5 of parallel timing characteristics for Parallel Interface Timing Diagram of 6800-series microprocessors. In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline processing is internally performed which requires the insertion of a dummy read before the first actual display data read. This is shown in Figure 4 below.
R/ W#(WR#)
E(RD#)
Data bus N Write column address Dummy read n Data read1
n+1 Data read2
n+2 Data read3
Figure 4 - Display data read back procedure - insertion of dummy read MPU Parallel 8080-series Interface The parallel interface consists of 16 bi-directional data pins (D0-D15), E (RD#), R/W#(WR#), D/C# and CS#. The E(RD#) input serves as data read latch signal (clock) when low, provided that CS# is low and high respectively. Display data or status register read is controlled by D/C#. R/W#(WR#) input serves as data write latch signal (clock) when high provided that CS# is low and high respectively. Display data or command register write is controlled by D/C#. Refer to Figure 6 of parallel timing characteristics for Parallel Interface Timing Diagram of 8080-series microprocessor. Similar to 6800-series interface, a dummy read is also required before the first actual display data read. MPU Serial Interface The serial interface consists of serial clock SCK, serial data SDA, D/C# and CS#. SDA is shifted into an 8-bit shift register on every rising edge of SCL in the order of D7, D6, ... D0. D/C# is sampled on every eighth clock and the data byte in the shift register is written to the Display Data RAM or command register in the same clock. Graphic Display Data RAM (GDDRAM) The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is 96 x 64 x 16bits. For mechanical flexibility, re-mapping on both Segment and Common outputs can be selected by software. For vertical scrolling of the display, an internal register storing display start line can be set to control the portion of the RAM data to be mapped to the display. Current Control and Voltage Control 10
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This block is used to derive the incoming power sources into the different levels of internal use voltage and current. VCC and VDD are external power supplies. VREF is reference voltage, which is used to derive driving voltage for segments and commons. IREF is a reference current source for segment current drivers. Segment Drivers/Common Drivers Segment drivers deliver 288 current sources to drive OLED panel. The driving current can be adjusted from 0 to 200uA with 256 steps. Common drivers generate voltage scanning pulse.
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COMMAND TABLE
Table 3 - Command table (D/C# =0, R/W#(WR#)=0, E (RD#)=1)
Hex 15 A[6:0] B[6: 0] 75 A[5:0] B[5:0] 81 A[7:0] 82 A[7:0] 83 A[7:0] 87 A[3:0] Command Set Column Address Description Second command A[7:0] sets the column start address from 0-95, POR=00d. Third command B[7:0] sets the column end address from 0-95 POR=95d. Second command A[6:0]sets the row start address from 0-63, POR=00d. Third command B[6:0] sets the row end address from 0-63, POR=63d. Double byte command to select 1 out of 256 contrast steps. Contrast increases as level increase. POR = 80H Same as above
Set Row Address
Set Contrast for Color A (Segment Pins :SA0 - SA95) Set Contrast for Color B (Segment Pins :SB0 - SB95) Set Contrast for Color C (Segment Pins :SC0 - SC95)
Same as above Set A[3:0] from 0000, 0001... to 1111 to adjust the master current attenuation factor from 1/16, 2/16... to 16/16. POR =1111b, for no attenuation. A[0]=0, Horizontal address increment (POR) A[0]=1, Vertical address increment A[1]=0, Column address 0 is mapped to SEG0 (POR) A[1]=1, Column address 131 is mapped to SEG0 A[2]=0, Reserve A[3]=0, Reserve A[4]=0, Scan from COM 0 to COM [N -1] A[4]=1, Scan from COM [N-1] to COM0. Where N is the Multiplex ratio. A[5]=0, Disable COM Split Odd Even (POR) A[5]=1, Enable COM Split Odd Even A[7:6]=00; 256 color format = 01; 65k color format(POR) Data formats are defined as CCCBBBAA for 256 color CCCCCBBB BBBAAAAA for 65k color
Master Current Control
A0 A[7:0]
Set Re-map & Data Format
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Hex
Command
Description
A1 A[5:0] A2 A[5:0]
Set Display Start Line
Set display RAM display start line register from 0-63. Display start line register is reset to 00H after POR. Set vertical scroll by COM from 0-63. The value is reset to 00H after POR. A4H=Normal Display (POR) A5H=Entire Display On, all pixels turn on at GS level 63 A6H=Entire Display Off, all pixels turns off A7H=Inverse Display The next command determines multiplex ratio N from 16MUX-64MUX, POR=63d (64MUX) AEH=Display off (POR) AFH=Display on The next 32 bytes of command set the current drive pulse width of gray scale level GS1, GS3, GS5 ...GS63 as below: A[7:0]=PW1, POR=1 B[7:0]=PW3, POR=5 C[7:0]=PW5, POR= 9 : : : AE[7:0]=PW61, POR=121 AF[7:0]=PW63, POR=125 Note: GS0 has no current drive. For GS2 GS4...GS62 : PWn = (PWn-1+PWn+1)/2 Max pulse width is 125
Set Display Offset
A4~A7
Set Display Mode
A8 A[5:0] AE~AF
Set Multiplex Ratio
Set Display On/Off
B8 A[7:0] --PW1 B[7:0] --PW3 C[7:0] --PW5 D[7:0] --PW7 : : : AE[7:0] --PW61 AF[7:0] --PW63
Set Gray Scale Table
E3
NOP
Command for No Operation
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COMMAND DESCRIPTIONS
Set Column Address This command specifies column start address and end address of the display data RAM. This command also sets the column address pointer to column start address. Set Row Address This command specifies row start address and end address of the display data RAM. This command also sets the row address pointer to row start address. Set Contrast for Color A, B, C This command is to set Contrast Setting of each color A, B and C. The chip has three contrast control circuits for color A, B and C. Each contrast circuit has 256 contrast steps from 00H to FFH. The segment output current increases linearly with the increase of contrast step. Master Current Control This command is to adjust the overall display brightness. The chip has 16 steps segment current reduction. The range is form 1/16[0000] to 16/16[1111]. POR is no current reduction [1111]. Set Re-map This command changes the mapping between the display data column address and segment driver, row address and common driver. It allows flexibility in layout during OLED module assembly. When A[5] is set as 0, COM outputs are in sequential format. When it is set as 1, COM outputs are in odd and even mode. See COM layouts in Figure 1 and 2. Set Data Format This command allows user to set different data formats for 256 color (8-bit) and 65k color (16-bit). Set Display Start Line This command is to set Display Start Line register to determine starting address of display RAM to be displayed by selecting a value from 0 to 63. Set Display Offset This is a double byte command. The next command specifies the mapping of display start line (it is assumed that COM0 is the display start line, display start line register equals to 0) to one of COM0-63. For example, to move the COM16 towards the COM0 direction for 16 lines, the 6-bit data in the second command should be given by 0010000. Set Display Mode This command is used to set Normal Display, Entire Display On, Entire Display Off and Inverse Display. Set Entire Display On forces the entire display to be at "GS63" regardless of the contents of the display data RAM. Set Entire Display Off forces the entire display to be at gray level "GS0" regardless of the contents of the display data RAM. Normal Display will turn the data to ON at the corresponding gray level. Set Multiplex Ratio This command switches default 1:64 multiplex mode to any multiplex mode from 16 to 64. Set Display On/Off This command turns the display on or off. When the display is off, the segment and common output are in high impedance state.
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Set Gray Scale Table This command is used to set the gray scale table for the display. Except GS0, which has no pre-charge and current drive, each GS level is programmed by the pulse width of current drive. NOP No Operation Command
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MAXIMUM RATINGS
Table 4 - Maximum Ratings (Voltage Reference to VSS)
Symbol VDD VCC VREF VCOMH Vin TA Tstg Parameter Supply Voltage Supply Voltage/Output voltage SEG/COM output voltage Input voltage Operating Temperature Storage Temperature Range Value -0.3 to +4 0 to 18 0 to 18 0 to 16 0 to 16 Vss-0.3 to Vdd+0.3 -30 to +85 -65 to +150 Unit V V V V V V C C
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Description.
DC CHARACTERISTICS
Table 5 - DC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD = 2.4 to 3.5V, TA = 25C)
Symbol
Vcc VDD VOH VOL VIH VIL ISLEEP ICC IDD
Parameter
Operating Voltage Logic Supply Voltage High Logic Output Level Low Logic Output Level High Logic Input Level Low Logic Input Level Sleep mode Current Vcc Supply Current VDD Supply Current Segment Output Current Setting VDD=2.7V, VCC=11V, IREF=10uA, All one pattern, Display on, Segment pin under test is connected with a 20K resistive load to Vcc. Segment output current uniformity
Test Condition
Min
7 2.4 0.9*V
DD
Typ
11 2.7 770 170 160 110 60 0
Max
18 3.5 VDD 0.1*V
DD
Unit
V V V V V V uA uA uA uA
Iout =100uA, 3.3MHz Iout =100uA, 3.3MHz Iout =100uA, 3.3MHz Iout =100uA, 3.3MHz VDD=2.7V, Display OFF, No panel attached VDD=2.7V, Display ON Contrast =FF, No panel attached VDD=2.7V, Display ON Contrast =FF, No panel attached Contrast = FF Contrast = AF Contrast = 5F Contrast = 00 Dev = (ISEG - IMID)/IMID IMID = (IMAX + IMIN)/2 ISEG[0:395] = Segment current at contrast = FF
0 0.8*V
DD
VDD 0.2*V
DD
0 -
5 -
ISEG
Dev
-
-
3
%
Adj. Dev RON_C Vcc Pwr
Adjacent pin output current uniformity (contrast = FF) Common Output On Resistance Booster output voltage (Vcc) Booster output power
Adj Dev = (I[n]-I[n+1]) / (I[n]+I[n+1]) VDD - VEE=11.7V, Iout=30mA; Vin=3V, L=22uH; R1=500Kohm; R2=50Kohm; Icc = 30mA(soaking) Vin=3V, L=22uH; Vcc = 10 V ~ 16V Rev 0.23 08/2003
10 -
2.0 23 -
-12 400
% V mW
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AC CHARACTERISTICS
Table 6 - AC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD = 2.4 to 3.5V, TA = 25C.)
Symbol
FOSC FFRM
Parameter
Oscillation Frequency of Display Timing Generator Frame Frequency for 64 MUX Mode
Test Condition
Vdd = 2.7V, IREF = 12uA 96RGB x 64 Graphic Display Mode, Display ON, Internal Oscillator Enabled
Min
-
Typ
0.97 FOSC X 1/(D*K*64)
Max
-
Unit
MHz Hz
D: divide ratio (POR =1) K: number of display clocks (POR = 125) Refer to command table for detail description
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Table 7 - 6800-Series MPU Parallel Interface Timing Characteristics (VDD - VSS = 2.4 to 3.5V, TA = -30 to 85C)
Symbol
tcycle tAS tAH tDSW tDHW tDHR tOH tACC PW CSL PW CSH tR tF
Parameter
Clock Cycle Time Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time Read Data Hold Time Output Disable Time Access Time Chip Select Low Pulse Width (read) Chip Select Low Pulse Width (write) Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time Fall Time
Min
300 0 0 40 15 20 120 60 60 60 -
Typ
-
Max
70 140 15 15
Unit
ns ns ns ns ns ns ns ns ns ns ns ns
D/C# tAS R/W# tAH
E tcycle CS# tF D0~D7(WRITE) tACC D0~D7(READ) Valid Data tOH PW CSL PW CSH
tR
tDHW
tDSW Valid Data
tDHR
Figure 5 - 6800-series MPU parallel interface characteristics
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Table 8 - 8080-Series MPU Parallel Interface Timing Characteristics (VDD - VSS = 2.4 to 3.5V, TA = -30 to 85C)
Symbol
tcycle tAS tAH tDSW tDHW tDHR tOH tACC PW CSL PW CSH tR tF
Parameter
Clock Cycle Time Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time Read Data Hold Time Output Disable Time Access Time Chip Select Low Pulse Width (read) Chip Select Low Pulse Width (write) Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time Fall Time
Min
300 0 0 40 15 20 120 60 60 60 -
Typ
-
Max
70 140 15 15
Unit
ns ns ns ns ns ns ns ns ns ns ns ns
D/C# tA WR# tAH
RD# tcycle CS# tF D0~D7(WRITE) tACC D0~D7(READ) Valid Data tOH PW CS tR tDSW Valid Data tDHR tDHW PW CSH
Figure 6 - 8080-series MPU parallel interface characteristics
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Table 9 - Serial Interface Timing Characteristics (VDD - VSS = 2.4 to 3.5V, TA = -30 to 85C)
Symbol
tcycle tAS tAH tCSS tCSH tDSW tDHW tCLKL tCLKH Clock Cycle Time Address Setup Time Address Hold Time Chip Select Setup Time Chip Select Hold Time Write Data Setup Time Write Data Hold Time Clock Low Time Clock High Time Rise Time Fall Time
Parameter
Min
250 150 150 120 60 100 100 100 100 -
Typ
-
Max
15 15
Unit
ns ns ns ns ns ns ns ns ns ns ns
tR
tF
D/C# tAS CS# tCSS tCLK SCK(D6) tF tDSW SDA(D7) Valid Data tR tDHW tcycle tAH tCSH tCLKH
CS#
SCK(D6) D7 D6 D5 D4 D3 D2 D1 D0
SDA(D7)
Figure 7 - Serial interface characteristics
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SSD1332
APPLICATION EXAMPLE
The configuration for 6800-parallel interface mode, externally VCC is shown in the following diagram: (VDD = 3.0V, external VCC = 12V, IREF = 10uA)
Color OLED Panel 96RGB x 64
COM62 . . COM0
SSD1332U1R1
NC VCC VCOMH NC D7~D0 E RW# DC# RES# CS# IREF BS2 BS1 VDD VP_C VP_B VP_A VBREF RESE FB VDDB GDR VSS NC
COM1 . . COM63
SA0 SB0 SC0 . . . . . . . . . . SA95 SB95 SC95
R1
C1 C2 C3
D7~D0
E
RW# DC# RES# CS#
VSS [GND]
Pin connected to MCU interface: D0~D7, E, R/W#, D/C#, RES#, CS# Pin internally connected to VDD: M/S#, CLS Pin internally connected to VSS: VSSB Pin internally connected to VCC: VREF Pin externally connected to VDD: BS2 Pin externally connected to VSS: BS1 Pin floated: VP_C, VP_B, VP_A, VBREF, RESE, FB, VDDB, GDR C1~C3: 4.7uF Voltage at IREF = VCC - 3V R1 = (Voltage at IREF - VSS) / IREF = 910K
Figure 8 - Application Example for SSD1332U1R1
21
SSD1332
Rev 0.23 08/2003
SOLOMON
Solomon Systech reserves the right to make changes without further notice to any products herein. Solomon Systech makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Solomon Systech does not convey any license under its patent rights nor the rights of others. Solomon Systech products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Solomon Systech product could create a situation where personal injury or death may occur. Should Buyer purchase or use Solomon Systech products for any such unintended or unauthorized application, Buyer shall indemnify and hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or manufacture of the part.
22
SOLOMON
Rev 0.23 08/2003
SSD1332

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